codyr8941 codyr8941

21-11-2022
Computers and Technology

contestada

for a direct-mapped cache design with a 64-bit address and byte-addressable memory, the following bits of the address are used to access the cache: tag index offset a. 63-9 8-5 4-0 b. 63-12 11-6 5-0 for each configuration (a and b): what is the block size (in bytes)? (5 pts) how many entries (blocks) does the cache have?

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